Parsing source code into a linear array

ABSTRACT

For parsing source code into a linear array, a method parses source code into a plurality of logic design elements. The method further identifies conditional logic for each logic design element. In addition, the method identifies computation logic for each logic design element. The method encodes each logic design element as a logic state of a plurality of logic states in a linear array. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method reduces the logic relationships to a Boolean equation. The method generates one of output source code and a hardware implementation from the Boolean equation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation-in-part application that claims priority to U.S.patent application Ser. No. 14/727,555 entitled “PARSING SOURCE CODEINTO A LINEAR ARRAY” and filed on Jun. 1, 2015 for M. David McFarland,which is incorporated herein by reference.

FIELD

The subject matter disclosed herein relates to a linear array and moreparticularly relates to parsing source code into a linear array.

BACKGROUND Description of the Related Art

The source code for a logic design defines logic elements and logicelement relationships. However, the complexity of the logic design mayincrease exponentially with the number of logic elements.

BRIEF SUMMARY

A method for parsing source code into a linear array is disclosed. Themethod parses source code of a multidimensional logical array logicdesign into a plurality of logic design elements. The method furtheridentifies conditional logic for each logic design element from theparsed source code. In addition, the method identifies computation logicfor each logic design element from the parsed source code. The methodidentifies one or more next state values for each logic design elementfrom the parsed source code. In addition, the method encodes each logicdesign element of the multidimensional logical array logic design as alogic state of a plurality of logic states in a linear array byassigning one or more present state values and the conditional logic foreach logic design element to each corresponding logic state, each logicstate comprising one or more binary output variables, one or more binaryinput variables, one or more minterms of the one or more binary inputvariables, one or more maxterms of the one or more minterms, the one ormore present state values, and the one or more next state values,wherein the plurality of logic states are displayed as a plurality offields in one or more combination maps. The method organizes theplurality of binary input variables into the plurality of fields in theone or more combination maps. The method identifies logic relationshipsof the logic design from relationship arrows in the one or morecombination maps using the linear array. The method further resolves thelogic relationships of the logic design using the one or morecombination maps of the linear array. The method reduces the logicrelationships of the logic design to a Boolean equation using the one ormore combination maps. The method generates one of output source codeand a hardware implementation from the Boolean equation. A programproduct and apparatus also perform the functions of the method.

BRIEF DESCRIPTION OF THE DRAWINGS

A more particular description of the embodiments briefly described abovewill be rendered by reference to specific embodiments that areillustrated in the appended drawings. Understanding that these drawingsdepict only some embodiments and are not therefore to be considered tobe limiting of scope, the embodiments will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings, in which:

FIG. 1A is a schematic block diagram illustrating one embodiment of asource code parsing process;

FIG. 1B is a text diagram illustrating one embodiment of a source codelogic design;

FIG. 1C is a schematic block diagram illustrating one embodiment ofhardware source code;

FIG. 1D is a drawing illustrating one embodiment of a multidimensionallogical array;

FIG. 1E is a schematic block diagram illustrating one embodiment of aproduction array implementation process;

FIG. 2A is a schematic block diagram illustrating one embodiment of alogic design;

FIG. 2B is a schematic block diagram illustrating one embodiment of alogic design element;

FIG. 2C is a schematic block diagram illustrating one embodiment of alogic transformation;

FIG. 2D is a schematic block diagram illustrating one embodiment ofinput data;

FIG. 2E is a schematic block diagram illustrating one embodiment of alinear array;

FIG. 2F is a schematic block diagram illustrating one embodiment of alogic state;

FIG. 2G is a schematic block diagram illustrating one embodiment offield data;

FIG. 2H is a schematic block diagram illustrating one embodiment ofassertion indicator data;

FIG. 2I is a schematic block diagram illustrating one embodiment ofconnection data;

FIG. 2J is a schematic block diagram illustrating one embodiment oflogic element data;

FIG. 2K is a schematic block diagram illustrating one embodiment of a docare array;

FIG. 2L is a schematic block diagram illustrating one embodiment of acallable execution block;

FIG. 2M is a schematic block diagram illustrating one embodiment of anintermediate linear array;

FIG. 2N is a schematic block diagram illustrating one alternateembodiment of an intermediate linear array;

FIG. 2O is a schematic block diagram illustrating one embodiment ofstate variables;

FIG. 2P is a schematic block diagram illustrating one embodiment of awhite box execution block;

FIG. 2Q is a schematic block diagram illustrating one embodiment of aproduction array;

FIG. 3A is a schematic block diagram illustrating one embodiment of atransform box;

FIG. 3B is a drawing illustrating one embodiment of a combination map;

FIG. 3C is a drawing illustrating one embodiment of a combination mapdisplay;

FIG. 3D is a drawing illustrating one embodiment of combination maplevels;

FIG. 3E is a text illustration showing one embodiment of source codewith delimiters;

FIG. 3F is a schematic drawing illustrating one embodiment of a finitestate machine diagram;

FIG. 3G is a schematic drawing illustrating one alternate embodiment ofa transform box;

FIG. 3H is a drawing illustrating one embodiment of generating anintermediate linear array from a combination map;

FIG. 3I is a schematic drawing illustrating one embodiment ofsemiconductor gates;

FIG. 4A is a schematic block diagram illustrating one embodiment of acomputer;

FIG. 4B is a schematic block diagram illustrating one alternateembodiment of a computer;

FIG. 5A is a schematic flowchart diagram illustrating one embodiment ofa source code parsing method;

FIGS. 5B-C are a schematic flowchart diagrams illustrating oneembodiment of a logic state encoding method;

FIG. 6 is a schematic block diagram illustrating one embodiment of astate chart;

FIG. 7A is a graph illustrating one embodiment of array complexity;

FIG. 7B is a graph illustrating one embodiment of speed improvementsfrom identifying DON'T CARE assertion values;

FIGS. 8A-B are a schematic flowchart diagram illustrating one embodimentof a production array implementation method; and

FIG. 9 is a schematic flowchart diagram illustrating one embodiment of adifference identification method.

DETAILED DESCRIPTION

As will be appreciated by one skilled in the art, aspects of theembodiments may be embodied as a system, method or program product.Accordingly, embodiments may take the form of an entirely hardwareembodiment, an entirely software embodiment (including firmware,resident software, micro-code, etc.) or an embodiment combining softwareand hardware aspects that may all generally be referred to herein as a“circuit,” “module” or “system.” Furthermore, embodiments may take theform of a program product embodied in one or more computer readablestorage medium storing machine readable code, computer readable code,and/or program code, referred hereafter as code. The computer readablestorage medium may be tangible, non-transitory, and/or non-transmission.The computer readable storage medium may not embody signals. In acertain embodiment, the storage devices only employ signals foraccessing code.

The computer readable storage medium may be a storage device storing thecode. The storage device may be, for example, but not limited to, anelectronic, magnetic, optical, electromagnetic, infrared, holographic,micromechanical, or semiconductor system, apparatus, or device, or anysuitable combination of the foregoing.

More specific examples (a non-exhaustive list) of the storage devicewould include the following: an electrical connection having one or morewires, a portable computer diskette, a hard disk, a random access memory(RAM), a read-only memory (ROM), an erasable programmable read-onlymemory (EPROM or Flash memory), a portable compact disc read-only memory(CD-ROM), an optical storage device, a magnetic storage device, or anysuitable combination of the foregoing. In the context of this document,a computer readable storage medium may be any tangible medium that cancontain or store a program for use by or in connection with aninstruction execution system, apparatus, or device.

Code for carrying out operations for embodiments may be written in anycombination of one or more programming languages including an objectoriented programming language such as Ada, Python, Ruby, Java,Smalltalk, C++, or the like, and conventional procedural programminglanguages, such as the “C” programming language, SQL, relay ladderlogic, or the like, and/or machine languages such as assembly languages.The code may execute entirely on the user's computer, partly on theuser's computer, as a stand-alone software package, partly on the user'scomputer and partly on a remote computer or entirely on the remotecomputer or server. In the latter scenario, the remote computer may beconnected to the user's computer through any type of network, includinga local area network (LAN) or a wide area network (WAN), or theconnection may be made to an external computer (for example, through theInternet using an Internet Service Provider).

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment. Thus, appearances of the phrases“in one embodiment,” “in an embodiment,” and similar language throughoutthis specification may, but do not necessarily, all refer to the sameembodiment, but mean “one or more but not all embodiments” unlessexpressly specified otherwise. The terms “including,” “comprising,”“having,” and variations thereof mean “including but not limited to,”unless expressly specified otherwise. An enumerated listing of itemsdoes not imply that any or all of the items are mutually exclusive,unless expressly specified otherwise. The terms “a,” “an,” and “the”also refer to “one or more” unless expressly specified otherwise.

Furthermore, the described features, structures, or characteristics ofthe embodiments may be combined in any suitable manner. In the followingdescription, numerous specific details are provided, such as examples ofprogramming, software modules, user selections, network transactions,database queries, database structures, hardware modules, hardwarecircuits, hardware chips, etc., to provide a thorough understanding ofembodiments. One skilled in the relevant art will recognize, however,that embodiments may be practiced without one or more of the specificdetails, or with other methods, components, materials, and so forth. Inother instances, well-known structures, materials, or operations are notshown or described in detail to avoid obscuring aspects of anembodiment.

Aspects of the embodiments are described below with reference toschematic flowchart diagrams and/or schematic block diagrams of methods,apparatuses, systems, and program products according to embodiments. Itwill be understood that each block of the schematic flowchart diagramsand/or schematic block diagrams, and combinations of blocks in theschematic flowchart diagrams and/or schematic block diagrams, can beimplemented by code. The code may be provided to a processor of ageneral-purpose computer, special purpose computer, or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions, which execute via the processor of the computer orother programmable data processing apparatus, create means forimplementing the functions/acts specified in the schematic flowchartdiagrams and/or schematic block diagrams block or blocks.

The code may also be stored in a storage device that can direct acomputer, other programmable data processing apparatus, or other devicesto function in a particular manner, such that the instructions stored inthe storage device produce an article of manufacture includinginstructions which implement the function/act specified in the schematicflowchart diagrams and/or schematic block diagrams block or blocks.

The code may also be loaded onto a computer, other programmable dataprocessing apparatus, or other devices to cause a series of operationalsteps to be performed on the computer, other programmable apparatus orother devices to produce a computer implemented process such that thecode which execute on the computer or other programmable apparatusprovide processes for implementing the functions/acts specified in theflowchart and/or block diagram block or blocks.

The schematic flowchart diagrams and/or schematic block diagrams in theFigures illustrate the architecture, functionality, and operation ofpossible implementations of apparatuses, systems, methods and programproducts according to various embodiments. In this regard, each block inthe schematic flowchart diagrams and/or schematic block diagrams mayrepresent a module, segment, or portion of code, which comprises one ormore executable instructions of the code for implementing the specifiedlogical function(s).

It should also be noted that, in some alternative implementations, thefunctions noted in the block may occur out of the order noted in theFigures. For example, two blocks shown in succession may, in fact, beexecuted substantially concurrently, or the blocks may sometimes beexecuted in the reverse order, depending upon the functionalityinvolved. Other steps and methods may be conceived that are equivalentin function, logic, or effect to one or more blocks, or portionsthereof, of the illustrated Figures.

Although various arrow types and line types may be employed in theflowchart and/or block diagrams, they are understood not to limit thescope of the corresponding embodiments. Indeed, some arrows or otherconnectors may be used to indicate only the logical flow of the depictedembodiment. For instance, an arrow may indicate a waiting or monitoringperiod of unspecified duration between enumerated steps of the depictedembodiment. It will also be noted that each block of the block diagramsand/or flowchart diagrams, and combinations of blocks in the blockdiagrams and/or flowchart diagrams, can be implemented by specialpurpose hardware-based systems that perform the specified functions oracts, or combinations of special purpose hardware and code.

The description of elements in each figure may refer to elements ofproceeding figures. Like numbers refer to like elements in all figures,including alternate embodiments of like elements.

FIG. 1A is a schematic block diagram illustrating one embodiment of asource code parsing process 100. The source code parsing process 100 mayparse and encode source code of a source code 140 into a linear array200. The source code 140 may describe logical operations that areimplemented in hardware, implemented in software, implemented asabstract logic, or combinations thereof. The hardware may besemiconductor logic, discrete logic, relay logic, or combinationsthereof.

The source code 140 typically specifies a plurality of inputs,conditions, actions, outputs, states and/or process flows, referred tohereinafter as logic elements. In addition, the source code 140specifies some of the interactions between the logic elements, referredto herein as logic element relationships.

The source code 140 maybe organized as source code. The source code maybe compiled as executable code that is executed by a processor. Forexample, C++ source code may be compiled and executed by an embeddedprocessor. Alternatively, the source code may be compiled andimplemented in hardware. For example, Verilog source code may becompiled and implemented into a semiconductor design.

A source code 140 with even a moderate number of logic elements resultsin a large number of logic element relationships. The logic elementrelationships may be an exponential function of the number of logicelements. As a result, the source code 140 may be intractablycomplicated.

By encoding the source code 140 in the linear array 200, the complexityof the source code 140 is greatly reduced in the linear array 200. Thelinear array 200 may be more easily analyzed and manipulated.

The embodiments described parse the source code of the source code 140with a parsing module 105. The encoding module 104 encodes the parsedsource code as logic states of the linear array 200 as will be describedhereafter. The linear array 200 may be employed to generate outputsource code that generates hardware 496. Alternatively, the linear array200 may be employed to generate output source code that is compiled tooperate the hardware 496 as will be described hereafter.

FIG. 1B is a text diagram illustrating one embodiment of a source codesource code 140. The source code source code 140 includes software linesof code (SLOC) 173 with conditional logic 172 that defines when variousactions 174 are taken. In the depicted embodiment, the actions 174 arecomputational statements. The source code source code 140 may becompiled to generate instructions for a processor or the like.

FIG. 1C is a schematic block diagram illustrating one embodiment of ahardware source code source code 140. In the depicted embodiment, thehardware source code source code 140 is a Verilog file. The hardwaresource code source code 140 includes conditional logic 172 that defineswhen various actions 174 are taken. In the depicted embodiment, theactions 174 are computational statements. The hardware source codesource code 140 may be compiled into a semiconductor device, a fieldprogrammable logic array (FPGA), or the like.

FIG. 1D is a drawing illustrating one embodiment of a multidimensionallogical array logic design 144 of the source code 140. For simplicity,the multidimensional logical array logic design 144 is shown for threelogic elements 176. As shown, the multidimensional logic array logicdesign 144 for only three logic elements 176 results in 2^(N) or 8 logicelement relationships. For even modest logic designs 140, the number oflogic element relationships quickly becomes intractable. The embodimentsdescribed herein encode logic designs 140 such as those illustratedFIGS. 1B-C into the linear array 200. The linear array 200 may beexamined to identify and define undefined logic element relationships aswill be described hereafter.

FIG. 1E is a schematic block diagram illustrating one embodiment of aproduction array implementation process 101. The process 101 mayidentify a plurality of white box execution blocks 131 in the sourcecode 140. The white box execution block 131 is described in more detailin FIG. 2P.

The process 101 may generate a callable execution block 151 for eachwhite box execution block 131. The callable execution block 151 isdescribed in more detail in FIG. 2L. In addition, the process 101 maygenerate one or more intermediate linear arrays 153 from the callableexecution blocks 151. The intermediate linear array 153 is described inFIG. 2M. The process 101 may further generate a production array 157from the intermediate linear arrays 153. In one embodiment, theproduction array 157 is a minimized production array 157. The productionarray 157 is described in FIG. 2Q.

The production array 157 may be implemented as a hardware implementation495 such as semiconductor gates 445. In addition, the production array157 may be implemented as minimized hardware output source code 435. Theproduction array 157 may further be implemented as minimized softwareoutput source code 435. In one embodiment, the production array 157 isimplemented as executable code 440.

FIG. 2A is a schematic block diagram illustrating one embodiment of asource code 140. The source code 140 may be organized as a datastructure in a memory. The source code 140 includes a plurality of logicdesign elements 130. Each logic design element 130 may include one ormore logic elements 176 and/or one or more logic element relationships.

The source code 140 maybe organized as a flat file comprising sourcecode, Boolean descriptions, logical relationships, state relationships,and the like. Each logic design element 130 may be a line or otherlogical division of the file. Alternatively, the logic design elements130 may define states 160, conditional logic 172, actions 174, orcombinations thereof.

FIG. 2B is a schematic block diagram illustrating one embodiment of alogic design element 130. The logic design element 130 may be organizedas a data structure in a memory. Each logic design element 130 may beparsed from the source code 140. In the depicted embodiment, the logicdesign element 130 includes an input identifier 132, conditional logic172, computational logic 134, and an end of state 136.

The element identifier 132 may uniquely identify the logic designelement 130. The element identifier 132 includes a file name. Inaddition, the element identifier 132 may comprise a range of linenumbers for a text file, a data structure reference number, orcombinations thereof.

The conditional logic 172 may define conditions that must be satisfiedin order to execute the computational logic 134. In addition, theconditional logic 172 may define an element identifier 132 if theconditions are not satisfied in order to execute the computational logic134. In one embodiment, the conditional logic 172 is always performed ifanother logic design element 130 branches to the current elementidentifier 132. In one embodiment, the conditional logic 172 includesone or more of nodes 178, paths 182, logic gates 142, binary outputs179, binary inputs 177, states 160, and actions 174.

The computational logic 134 may specify actions 174 that are performedif the conditional logic 172 is satisfied. The actions 174 may includeone or more computational statements. Alternatively, the actions 174 mayinclude one or more of nodes 178, paths 182, logic gates 142, binaryoutputs 179, binary inputs 177, and states 160. In addition, thecomputational logic 134 may assert and/or deassert one or more binaryoutput variables and/or one or more next state values. The end of state136 may indicate an end of the conditional logic 172 and thecomputational logic 134 associated with the element identifier 132.

FIG. 2C is a schematic block diagram illustrating one embodiment of alogic transformation 150. The logic transformation 150 may be generatedfrom the logic design element 130. The logic transformation 150 maybeorganized as a data structure in a memory. In the depicted embodiment,the logic transformation 150 includes a logic transformation identifier155, binary output variables 225, next state values 230, and input data160.

The binary output variables 225 maybe control signals such as binaryoutputs 179. In addition, the binary output variables 225 may identifydata structures such as numerical values, alphanumeric values, logicalvalues, dates, times, and the like. In one embodiment, the logic designelement 130 is parsed to identify each binary output variable 225 fromthe computational logic 134.

The next state values 230 may define logical states. In one embodiment,the next state values 230 comprise an element identifier 132 for a logicdesign element 130. In addition, the next state values 230 may includeone or more binary state values as will be described hereafter.

The input data 160 may define inputs that generate the binary outputvariables 225 and the next state values 230. In one embodiment, inputdata 160 is generated for each binary output variable 225 and each nextstate value 230.

FIG. 2D is a schematic block diagram illustrating one embodiment ofinput data 160. The input data 160 maybe organized as a data structurein a memory. In the depicted embodiment, the input data 160 includes aninput identifier 165 and a plurality of binary input variables 215.

The input identifier 165 may uniquely identify the input data 160. Thebinary input variables 215 may be control signals such as binary inputs177. Alternatively, the binary input variables 215 may identify datastructures such as numerical values, alphanumeric values, logicalvalues, dates, times, and the like.

FIG. 2E is a schematic block diagram illustrating one embodiment of alinear array 200. The linear array 200 may be generated from the logictransformation 150. The linear array 200 maybe organized as a datastructure in a memory. The linear array 200 includes a plurality oflogic states 205.

FIG. 2F is a schematic block diagram illustrating one embodiment of alogic state 205. The logic state 205 maybe organized as a data structurein a memory. The logic state 205 includes a logic state identifier 210,one or more binary input variables 215, one or more binary outputvariables 225, one or more next state values 230, one or more presentstate values 220, one or more maxterms 235, one or more minterms 240,and a state transitions value 343.

The logic state identifier 210 may uniquely identify the logic state205. The logic state identifier 210 may include a label, a mnemonic, orthe like. In addition, the logic state identifier 210 may include acorresponding logic transformation identifier 155 for the logictransformation 150 that corresponds to the logic state 205.

The binary output variables 225 may include each binary output variable225 from the source code 140. Alternatively, the binary output variables225 may include each binary output variable 225 identified for thecorresponding logic transformation 150. In one embodiment, each binaryoutput variable 225 is assigned an identifier such as a label, a logicalrepresentation, an index value, or the like.

The binary input variables 215 may include each binary input variable215 from the source code 140. In addition, the binary input variables215 may include each binary input variable 215 identified for thecorresponding logic transformation 150. NOT logic 340 may be associatedwith each binary input variable 215. The NOT logic 340 indicates whetheran inverse of the binary input variable 215 is asserted. In oneembodiment, each binary input variable 215 is assigned an identifiersuch as a label, a logical representation, an index value, or the like.

The present state values 220 may be binary values that uniquely definethe logic state 205 as a binary value. The present state values 220 mayuniquely describe the logic state identifier 210. The present statevalues 220 for each logic state 205 may be associated with a logictransformation identifier 155. In one embodiment, the present statevalues 220 may be selected reduce the complexity of the source code 140.In one embodiment, each present state value 220 is assigned anidentifier such as a label, a logical representation, an index value, orthe like.

The next state values 230 may define one or more next states that arebranched to as a function of the binary input variables 215. The nextstate values 230 may be a binary encoding of the next state values 230of the logic transformation 150. In one embodiment, each next statevalue 230 is assigned an identifier such as a label, a logicalrepresentation, an index value, or the like.

Each minterm 240 may be a binary product or logical AND of one or morebinary input variables 215 and/or one or more present state values 220.Alternatively, each minterm 240 may be a binary product of one or moremaxterms 235. In one embodiment, each minterm 240 is assigned anidentifier such as a label, a logical representation, an index value, orthe like.

Each maxterm 235 may be a binary sum or logical OR of one or moreminterms 240. Alternatively, each maxterm 235 may be a binary sum of oneor more binary input variables 215 and/or one or more present statevalues 220. In one embodiment, each maxterm 235 is assigned anidentifier such as a label, a logical representation, an index value, orthe like.

The state transitions value 343 may record a number of state transitionsthat have been traversed from a current logic state 205 to subsequentlogic states 205. A state transition transitions active control from thecurrent logic state 205 to a subsequent logic state 205. For example,the current logic state 205 STATE00 may transition active control of adevice or computer to subsequent state 205 STATE01.

In one embodiment, the state transitions value 343 is incremented eachtime a state transition from the current logic state 205 is traversed.Alternatively, the state transitions value 343 records a total number ofstate transitions from the current logic state 205 to subsequent logicstates 205.

The plurality of logic states 205 in the linear array 200 represents themultidimensional array of the source code 140 in a form that is moreeasily manipulated and analyzed. As a result, logic elementrelationships may be identified, analyzed, and resolved as will bedescribed hereafter.

FIG. 2G is a schematic block diagram illustrating one embodiment offield data 250. The field data 250 describes a field in the combinationmap. The field data 250 maybe organized as a data structure in a memory.In the depicted embodiment, the field data 250 includes a fieldidentifier 165, one or more logic state identifiers 210, and one or morebinary input variables 215.

The field identifier 165 may uniquely identify the field in thecombination map. The logic state identifier 210 may identify a logicstate 205 associated with the field. Each field may represent at leastone single logic state 205. The binary input variables 215 may indicatewhich of the binary input variables 215 for the logic state 205 isassociated with the field.

FIG. 2H is a schematic block diagram illustrating one embodiment ofassertion indicator data 170. The assertion indicator data 170 mayindicate whether a logic element 176 is asserted. The assertionindicator data 170 may be organized as a data structure in a memory. Inthe depicted embodiment, the assertion indicator data 170 includes alogic element identifier 450, an assertion indicator 295, and anassertion value 290.

The logic element identifier 450 associates the assertion indicator data170 with a logic element 176. The assertion value 290 specifies whetherbinary input variables 215, present state values 220, minterms 240,maxterms 235, binary output variables 225, next state values 230, statevalues 315 and other logic elements 176 are asserted, deasserted, aDON'T CARE, undefined, or unknown.

In one embodiment, the assertion indicator 295 is of an indicator typeselected from the group consisting of a color, a label, an arrow, anicon, hashing, and motion. For example, the indicator type may be acolor with blue indicating that a field is asserted and read indicatingthat the field is deasserted.

FIG. 2I is a schematic block diagram illustrating one embodiment ofrelationship arrow data 175. The relationship arrow data 175 may definea relationship arrow between fields of the combination map as will bedescribed hereafter. The relationship arrow data 175 maybe organized asa data structure in a memory. In the depicted embodiment, therelationship arrow data 175 includes a connection identifier 255, asource field 260, a destination field 265, and the assertion indicatordata 170.

The connection identifier 255 uniquely identifies a connection betweenthe source field 260 and the destination field 265. The connectionidentifier 255 may be a label, an index, or the like.

The source field 260 may identify a first field that defines a firstlogical element relationship. The destination field 265 may identify oneor more second fields that have second logical element relationshipsthat include the first logical element relationship. For example, thesource field 260 may define first binary input variables 215 that areincluded the minterms 240 of the destination field 265. The destinationfield 265 may be a combination map. The assertion indicator data 170 mayindicate if the source field 260 and/or the connection between thesource field 260 and the destination field 265 are asserted.

FIG. 2J is a schematic block diagram illustrating one embodiment oflogic element data 185 for a logic element 176. The logic element data185 maybe organized as a data structure in memory. In the depictedembodiment, the logic element data 185 includes a logic elementidentifier 450, a logic element type 455, one or more input identifiers456, one or more output identifiers 457, a partition identifier 459, anexecution time 377, and a package identifier 461.

The logic element identifier 450 may uniquely identify the logicelement. The logic element identifier 450 may be a label, an index, orthe like.

The logic element type 455 may specify a type such as a binary inputvariable 215, a binary output variable 225, the minterm 240, a maxterm235, a present state value 220, a next state value 230, not logic 340, astate transition between logic states 205, and the like. Alternatively,the logic element type 455 may specify a logic state 205, a state 160, asoftware variable, conditional logic 172, computational logic 134, anaction 174, a node 178, a path 182, or the like.

The input identifiers 456 may list the logic element identifiers 450 ofinputs such as binary inputs 177 to the logic element. The outputidentifiers 457 may list the logic element identifiers 450 of logicelements receiving outputs from the logic element.

The partition identifier 459 may specify a partition that the logicelement is assigned to. A partition may be a device design, hardwaredesign elements for a device, software design elements for a device, orthe like. For example, the partition identifier 459 may specify thelogic element 176 is assigned to a software design partition.Alternatively, the partition identifier 459 may specify that the logicelement 176 is assigned to a hardware design partition.

The execution time 377 may specify one or more of a minimum time for astate transition, a maximum time for a state transition, an average timefor a state transition, a mean time for a state transition, a mediumtime for a state transition, the simulation generated time for a statetransition, or the like.

The package identifier 461 may specify a destination package for thelogic element. The destination package may be a defined package or acomputational package. The defined package and the computational packagemay be used to validate the linear array 200.

FIG. 2K is a schematic block diagram illustrating one embodiment of a docare array 139. The do care array 139 may be organized as a datastructure in a memory. The do care array 139 may include a plurality ofdimensions 138. The do care array 139 may include a dimension 138 forall present state values 220 and each binary input variable 215 of thecallable execution block 131. In addition, the do care array 139includes a binary do care/don't care value for each combination ofpresent state values 220 and binary input variable instances 215 in adimension 138.

FIG. 2L is a schematic block diagram illustrating one embodiment of acallable execution block 151. The callable execution block 151 may beorganized as a data structure in a memory. In one embodiment, thecallable execution block 151 includes the logic transformationidentifier 155, the binary output variables 225, the next state values230, and the input data 160 of the logic transformation 150 of FIG. 2C.In addition, the callable execution block 151 may include the do carearray 139, state variables 133, the present state values 220, callablesource code parameters 137, and the binary input variables 215. Thestate variables 133 are described in more detail in FIG. 2O.

The callable source code parameters 137 may associate one or more of thepresent state values 220 and the binary input variables 215 with acallable mnemonic. The callable mnemonic may be employed to define thepresent state values 220 and/or the binary input variables 215. Thecallable source code parameters 137 may be globally maintained.

FIG. 2M is a schematic block diagram illustrating one embodiment of anintermediate linear array 153. The intermediate linear array 153 may beorganized as a data structure in a memory. In one embodiment, anintermediate linear array 153 is generated for each callable executionblock 151. In the depicted embodiment, the intermediate linear array 153includes a plurality of entries 152. Each entry 152 includes a uniquecombination of the present state values 220 and the binary inputvariable instances 215 that are do cares as indicated by the docare/don't care value 141. The present state values 220 and the binaryinput variable instances 215 that are don't cares are excluded from theintermediate linear array 153.

FIG. 2N is a schematic block diagram illustrating one alternateembodiment of an intermediate linear array 153. In the depictedembodiment, each entry 152 includes the logic state 205 for the uniquecombination of the present state values 220 and the binary inputvariable instances 215 that are do cares as indicated by the docare/don't care value 141. The logic states 205 that include presentstate values 220 and the binary input variable instances 215 that aredon't cares are excluded from the intermediate linear array 153.

FIG. 2O is a schematic block diagram illustrating one embodiment ofstate variables 133. The state variables 133 may be organized as a datastructure in a memory. In one embodiment, each state variable 133 isBoolean. For example, each state variable 133 may be a one or zero.Alternatively, each state variable 133 may be true or false. In oneembodiment, each state variable 133 is asserted or deasserted. The statevariables 133 may be associated with a corresponding white box executionblock 131. Each state variable 133 may only be modified by thecorresponding white box execution block 131 and may be modified at leastonce by the corresponding white box execution block 131. In addition,each state variable 113 persists from one execution of a white boxexecution block 131 to another execution of the white box executionblock 131. The state variables 113 are modified as a function of thebinary input variables 215 and the present state values 220.

FIG. 2P is a schematic block diagram illustrating one embodiment of thewhite box execution block 131. The white box execution block 131 may beorganized as a data structure in a memory. In the depicted embodiment,the white box execution block 131 includes the element identifier 132,the conditional logic 172, the computational logic 134, and the endstate 136 of the logic design element 130. In addition, the white boxexecution block 131 may include a begin block delimiter 344, an endblock delimiter 346, one or more logically atomic code blocks 341, andthe state variables 133.

The white box execution block 131 may be identified from the source code140. Each white box execution block 131 may be delimited by the beginblock delimiter 344 and the end block delimiter 346 in the source code140.

In one embodiment, the conditional logic 172 is used to identify one ormore logically atomic code blocks 341. Each logically atomic code block341 may be a collection of SLOC 173 that is executed sequentially from acommon logical condition 172. In addition, logically atomic code blocks341 that modify the white box execution block 131 may be appended to thewhite box execution block 131. In one embodiment, each logically atomiccode block 341 that begins within the white box execution block 131 alsoends within the white box execution block 131.

FIG. 2Q is a schematic block diagram illustrating one embodiment of aproduction array 157. The production array 157 maybe organized as a datastructure in a memory. The production array 157 may comprise a pluralityof entries 152 from one or more intermediate linear arrays 153. In oneembodiment, the production array 157 is generated by minimizing andjoining the one or more intermediate linear arrays 153.

FIG. 3A is a schematic block diagram illustrating one embodiment of atransform box 330. The transform box 330 represents one or more logicstates 205 as combinatorial logic. The transform box 330 allowsundefined logic element relationships to be identified and resolved.Each transform box 330 may be associated with at least one logic state205 and the field data 250 for the at least one logic state 205. Thetransform box 330 may be presented as a graphical user interface (GUI)on display. The elements of the transform box 330 may be manipulated byuser. In the depicted embodiment, the elements of the transform box 330include state values 315, the present state values 220, the next statevalues 230, the binary input variables 215, the NOT logic 340, one ormore minterms 240, and one or more maxterms 235. In the depictedembodiment, the transform box 330 shows sum of products logic.Alternatively, the transform box 330 may display product of sums logic.

In one embodiment, only one maxterm 235 is displayed at a given time.Alternatively, each maxterm 235 for the logic state 205 may be displayedat a given time. Each maxterm 235 is represented as a logical sum of oneor more minterms 240. Each maxterm 235 defines one or more of a nextstate value 230 and a binary output variable 225. Alternatively, onlyone minterm 240 may be displayed for product of sums logic.

Each minterm 240 may be displayed as a function of one or more binaryinput variables 215 and the NOT logic 340 associated with the binaryinput variables 215. In addition, each minterm 240 may be displayed as afunction of the present state values 220.

The state values 315 may indicate previous next state values 230 thatdefine the present state values 220. The next state values 230 define anext logic state 205. The binary output variables 225 define the actions174 of the logic state 205.

Connection lines 310 may show the logical relationship of the binaryinput variables 215 and present state values 220 to minterms 240 and NOTlogic 340. In addition, the connection lines 310 may show the logicalrelationship of the minterms 240 to the maxterms 235. Assertionindicator data 170 may define an assertion value for each connectionline 310. A Boolean expression may be derived from the connection lines310, binary input variables 215, present state values 220, NOT logic340, minterms 240, and maxterms 235.

In one embodiment, a user may modify a logic state 205 by editing thedisplayed present state values 220, binary input variables 215, NOTlogic 340, minterms 240, maxterms 235, next state values 230, binaryoutput variables 225, and connection lines 310.

FIG. 3B is a drawing illustrating one embodiment of a combination map190. In the depicted embodiment, fields 125 are shown for four stateinputs 465. Each state input 465 is one of a binary input variable 215and a present state value 220. Each field 125 is associated with uniquefield data 250. Each field 125 may represent a logic state 205.Alternatively, each field 125 may represent a plurality of binary inputvariables 215 as will be shown in FIG. 3D.

In one embodiment, state inputs 465 are automatically organized into theplurality of fields 125. For example, present state values 220 may beassigned to fields of higher level combination maps 190 while binaryinput variables 215 may be assigned to lower level combination maps 190.In addition, binary input variables 215 that defined in for a largernumber of minterms 235 may be assigned to higher level combination maps190. In one embodiment, binary input variables 215 that are defined withdiffering assertion values 290 for a larger number of minterms 235 areassigned to higher level combination maps 190.

FIG. 3C is a drawing illustrating one embodiment of a combination mapdisplay 480. A combination map 190 is displayed to the user such as onthe display of a computer. State input labels 485 are shown for eachstate input 465 of FIG. 3B. Assertion bars 460 indicate whether eachstate input 465 is asserted or deasserted. Each field 125 of FIG. 3Bdisplays a next state 470 if the state inputs 465 for the field 125 areasserted. The next state 470 may be next state values 230, a logic stateidentifier 210, or combinations thereof. Alternatively, the next state470 may indicate another combination map 190 with binary input variables215 that determine if the field 125 is asserted.

If the state inputs 465 indicated by the state input labels 485 arepresent state values 220, each field 125 may represent a logic state205. A user may be prompted to enter a logic state identifier 210 foreach logic state 205.

In addition, each field 125 may define an assertion value for the one ormore binary output variables 225. The user may be prompted to define theassertion value 290 of a binary output variable 225 for each field 125and/or each logic state 205.

In the depicted embodiment, a first field 125 a is defined as assertedas a result of each the state inputs 465 identified by the state inputlabels 485 being asserted. As a result, upon completion of the logicstate 205 defined by the present state values 220, the next state values230 associated with the next state 470 will be asserted.

FIG. 3D is a drawing illustrating one embodiment of combination maplevel display 475. A plurality of combination maps 190 are shown asthough displayed on the display of the computer. Each field 125 maycorrespond to a logic state 205, one or more minterms 240, one or moremaxterms 240, or combinations thereof.

In one embodiment, each combination map 190 on a lower level, such ascombination maps 190 b-d, corresponds to only one field 125 on acombination map 190 of an upper level, such as combination map 190 a.The state input labels 485 may indicate the state inputs 465 such aspresent state values 220 and binary input variables 215 that define thefields 125. Assertion values 290 are also indicated for the state inputs465.

In one embodiment, the fields 125 of the upper level combination maps190 correspond to logic states 205. For example, each field 125 of thetop-level combination map 190 a may correspond to a logic state 205.Alternatively, the fields 125 of two or more upper level combinationmaps 190 may correspond to logic states 125. The state inputs 465 of theupper level combination maps 190 may be present state values 230 thatindicate which logic state 205 is active.

A first field 125 a of a first combination map 190 a may be defined by asecond combination map 190 b as indicated by a first relationship arrow490 a. Each relationship arrow 490 may connect a field 125 of an upperlevel combination map 190 to a lower level combination map 190. Thefirst combination map 190 a may represent the present state values 220 aand b.

The second combination map 190 b may represent the Boolean equationcef′. A second relationship arrow 490 b may indicate that a second field125 b of the second combination map 190 b is defined by a fourthcombination map 190 d. The fourth combination map 190 d may representthe Boolean equation g′h′i as indicated by asserting a fifth filed 125e. A third relationship arrow 490 c may indicate that a third field 125c is defined by a third combination map 190 c. The third combination map190 c may represent the Boolean equation ghi as indicated by asserting afourth field 125 d. In the depicted embodiment, the combination maplevel display 475 represents the Boolean equation 126X=a′b(c′d′ef′ghi+c′def′g′h′i).

The plurality of combination maps 190 forms a multilevel display format.The multilevel display format has a top display level as illustrated bythe first combination map 190 a and at least one lower display levels asillustrated by the second and third combination maps 190 b-c.

Each combination map 190 includes state input labels 485 that identifythe state inputs 465 for the combination map 190. Relationship arrows490 show the logical relationship between a combination map 190 and afield 125. The relationship arrows 490 may be defined by therelationship arrow data 175.

In one embodiment, relationship arrows 490 link a first field 125 a withsuccessive combination maps 190 at successive display levels. Therelationship arrows 490 indicate a logical relationship between thefields 125.

A combination of first binary input variables 215 and/or present statevalues 220 for a first field 125 a may be identified by selecting thefirst field 125 a of a combination map 190 a at first display level. Inresponse to selecting the first field 125 a, additional combinations ofsecond binary input variables 215 in a successive combination map 190that logically define the first field 125 a may be identified. Thecombination map 190 of the second binary input variables 215 may be at asuccessive display level lower than the first display level.

In one embodiment, combination maps 190 of additional binary inputvariables 215 that logically define the selected first field 125 a aredisplayed on combination maps 190 at each successive level until thelast display level is reached. In one embodiment, the combination maps190 may be logically collapsed. A binary output variable 225 may beassigned to the combination of all binary input variables 215 on eachdisplay level of the combination maps 190 for the selected first field125 a. In addition, the combination of all binary input variables 215 oneach display level of the combination maps 190 may be converted into alogical expression 126.

FIG. 3E is a text illustration showing one embodiment of source code 342with delimiters. The exemplary source code 342 of FIG. 1C is shown afterbeing parsed by the parsing module 104. The source code 342 includeslogically atomic code blocks 341. Delimiters including begin blockdelimiters 344, end block delimiters 346, and destination delimiters 348are inserted.

A begin block delimiter 344 may be inserted to mark the beginning of alogic design element 130. A logic design element 130 may include alogically atomic block of code between conditional logic 172, with noconditional logic 172 between the conditional logic 172. The conditionallogic 172 is depicted as a conditional statement. In one embodiment, abegin block delimiter 344 is inserted before each conditional logicconditional statement.

The begin block delimiter 344 may include a block identifier such as alabel, an alphanumeric stream, and/or an index. In the depictedembodiment, letters identify each logic design element.

An end block delimiter 346 may be inserted to mark the end of a logicdesign element 130. Each end block delimiter 346 may include a blockidentifier. In the depicted embodiment, letters identify each logicdesign element.

A destination delimiter 348 indicates a logic design element 130 thatbecomes active in response to conditional logic 172 being one ofsatisfied or not satisfied. In the depicted embodiment, the destinationdelimiter 348 indicates a destination if the conditional logic 172 issatisfied. In one embodiment, a next logic design element 130 in thesource code 342 becomes active if the conditional logic 172 of the logicdesign element is not satisfied.

FIG. 3F is a schematic drawing illustrating one embodiment of a finitestate machine diagram 149. In the depicted embodiment, the finite statemachine diagram 149 is generated for exemplary source code 140. Thefinite state machine diagram 149 includes a plurality of states 143.State transitions 147 between the states 143 are based on the presentstate values 220 and the binary input variables 215 for the state 143.

FIG. 3G is a schematic drawing illustrating one alternate embodiment ofa transform box 330. The transform box 330 implements the exemplarysource code 140 of FIG. 3F. The present state values 220 are stored inthe states storage 221 and represented hereafter as Field_0. The binaryinput variables 215 are represented as Field_1. The transform box 330generates next state values 230 that are stored in the states storage121 and an exemplary binary output variable “FIRE” 225.

FIG. 3H is a drawing illustrating one embodiment of generating anintermediate linear array 153 from a combination map 190. Combinationmaps 190 for present state values Field_0 220 and binary input variablesField_1 215 of FIG. 3G are shown.

FIG. 3I is a schematic drawing illustrating one embodiment ofsemiconductor gates 445. In the depicted embodiment, a production array157 generated from the intermediate linear array 153 of FIG. 3H isimplemented in the semiconductor gates 445. In one embodiment, theproduction array 157 is generated using a plurality of standard cells123. Each standard cell 123 may have at most three gate delays.

FIG. 4A is a schematic block diagram illustrating one embodiment of acomputer 400. The encoding module 104 and the parsing module 105 may beembodied in the computer 400. In the depicted embodiment, the computer400 includes a processor 405, a memory 410, communication hardware 415,and a display 420. The memory 410 may be a semiconductor storage device,a hard disk drive, an optical storage device, a micromechanical storagedevice, or combinations thereof. The memory 410 may store code. Theprocessor 405 may execute the code. The communication hardware 415 maycommunicate with other devices. In addition, the communication hardware415 may receive inputs from a user. The display 420 may communicate datato the user.

FIG. 4B is a schematic block diagram illustrating one alternateembodiment of a computer 400. In the depicted embodiment, the computer400 includes a plurality of computational resources 425. In oneembodiment, each computational resource 425 includes a processor 405 anda memory 410. In addition, each computational resource 425 may includecommunication hardware 415. The computational resources 425 required tosatisfy a minimization policy may be determined and the computationalresources 425 allocated that satisfy the minimization policy.

FIG. 5A is a schematic flowchart diagram illustrating one embodiment ofa source code parsing method 500. The method 500 may be performed by theprocessor 405 and/or parsing module 105. Alternatively, the method 500may be performed by the computer readable storage medium such as thememory 410. The memory 410 may store code that is executed by theprocessor 405 to perform the functions of the method 500.

The method 500 starts, and in one embodiment, the processor 405identifies 505 one or more nested loops of conditional logic 172. Theprocessor 405 may identify 505 an end for each statement of conditionallogic 172.

The processor 405 may further identify 510 a logic design element 130.In one embodiment, the logic design element 130 is a next conditionalstatement of conditional logic 172. The processor 405 may further insert515 a begin block delimiter 344 adjacent to the conditional statement ofconditional logic 172. For example, the processor 405 may insert 515 thebegin block delimiter 344 before a “switch” or “case” conditionalstatement of conditional logic 172.

In addition, the processor 405 may insert 520 an end block delimiter346. The end block delimiter 346 may be inserted 520 adjacent to thecorresponding end for the conditional logic 172. For example, theprocessor 405 may insert 520 the end block delimiter 346 after the endfor a last statement of the conditional logic 172.

In one embodiment, the processor 405 inserts 525 one or more destinationdelimiters 348. In one embodiment, a destination delimiter 348 isinserted 525 after the statement of conditional logic 172. In addition,the destination delimiter 348 may indicate that the logic state 205specified by the destination delimiter 348 is activated if the statementof conditional logic 172 is either satisfied or not satisfied.

In one embodiment, the destination delimiter 348 is inserted 525adjacent to the end of the statement of conditional logic 172. Thedestination delimiter 348 may indicate a next logic state 205 to becomeactive after the logic state 205 for the current statement ofconditional logic 172 is completed.

The processor 405 may determine 530 if all logic design elements 130have been identified. If all logic design elements 130 have not beenidentified, the processor 405 loops to identify 510 the next logicdesign element 130. If all logic design elements 130 have beenidentified, the method 500 ends.

FIG. 5B is a schematic flowchart diagram illustrating one embodiment ofa logic state encoding method 700. The method 700 may encode the parsedsource code 140 as one or more logic states 205 of the linear array 200.The method 700 may be performed by the processor 405 and/or encodingmodule 104. Alternatively, the method 700 may be performed by thecomputer readable storage medium such as the memory 410. The memory 410may store code that is executed by the processor 405 to perform thefunctions of the method 700.

The method 700 starts, and in one embodiment, the processor 405 parses705 the source code 140 of a multidimensional logical array logic design144 into a plurality of logic design elements 130. The processor 405 maysegment the source code 140 into a plurality of logic design elements130 as described in FIG. 5A. The processor 405 may further parse 705 aplurality of white box execution blocks 131 from the source code 140.

The processor 405 may identify 710 the conditional logic 172 in eachlogic design element 130 from the parsed source code 140. Theconditional logic 172 may be identified from the begin block delimiters344 and the end block delimiters 346. In addition, the processor 405 mayidentify 710 the input data 160 for the logic transformation 150 fromthe conditional logic 172 and the actions 174.

In addition, the processor 405 may identify 715 computational logic 134in each logic design element 130 from the parsed source code 140. In oneembodiment, the computational logic 134 is identified from the actions174 of the source code source code 140. The processor 405 may identify715 the binary output variables 225 for the logic transformation 150from the computational logic 134. In addition, the processor 405 mayidentify 715 the input data 160 for the logic transformation 150 fromthe computational logic 134.

In one embodiment, the processor 405 identifies 720 the end of state 136for each logic design element 130. The end of state 136 may beidentified from the end block delimiter 346. Alternatively, the end ofstate 136 may be an end of a conditional statement, an end of a sequenceof instructions that are executed in response to conditional logic 172being satisfied, or the like.

The processor 405 may indicate 725 assertion values for the binary inputvariables 215, the present state values 220, the binary output variables225, and the next state values 230. In one embodiment, an assertionindicator 295 is associated with each of the binary input variables 215,the present state values 220, the binary output variables 225, and thenext state values 230.

The processor 405 may identify 727 one or more next state values 230 foreach logic design element 130 from the parsed source code 140. The nextstate values 230 for the logic transformation 150 may be identified 727from the conditional logic 172 and the destination delimiters 348.

The processor 405 may encode 730 the logic state 205 from the logictransformation 150. In one embodiment, the logic state 205 is assignedpresent state values 220. The present state values 220 may be assignedto minimize the minterms 240 and the maxterms 235 that generate thepresent state values 220. In addition, the next state values 230 for thelogic state 205 may be generated from the next state values 230 of thelogic transformation 150. In one embodiment, the next state values 230for the logic state 205 are equivalent to the next state values 230 ofthe logic transformation 150.

The binary input variables 215 of the logic state 205 may be generatedfrom the binary input variables 215 of the logic transformation 150. Inone embodiment, the binary input variables 215 of the logic state 205are equivalent to the binary input variables 215 of the logictransformation 150.

The processor 405 may further encode 730 the logic state 205 bygenerating the minterms 240 and the maxterms 235 from the computationallogic 134. In one embodiment, the minterms 240 in the maxterms 235 arestructured to be logically equivalent to the computational logic 134.

The processor 405 may further assign one or more maxterms 235 to eachbinary output variable 225 and/or each next state value 230.Alternatively, the processor 405 may assign one or more minterms 240 toeach binary output variable 225 and/or each next state value 230.

The processor 405 may organize 735 the plurality of binary inputvariables 215 into the plurality of fields 260/265 in the one or morecombination maps 190. The plurality of logic states 205 may be displayed740 as a plurality of fields 260/265 in one or more combination maps190. In one embodiment, the processor 405 displays 740 the plurality oflogic states 205 as a state chart 600. The state chart 600 may showtransitions between each logic state 205 as shown in FIG. 6. Inaddition, the state chart 600 may show one or more conditions for thetransitions.

The processor 405 may further identify 745 logic relationships of thelogic design 144 using the one or more combination maps 190 of thelinear array 200. The logic relationships may be identified from therelationship arrows 490. In the one or more combination maps 190 usingthe linear array 200. In addition, the processor 405 may analyze 750 thelogic relationships of the logic design 144 using the one or morecombination maps of the linear array 200.

The processor 405 may resolve 755 the logic relationships of the logicdesign 144 using the one or more combination maps 190 of the lineararray 200. The processor 405 may further reduce 760 the logicrelationships of the logic design 144 to a Boolean equation 126 usingthe one or more combination maps 190.

The processor 405 may generate 765 output from the Boolean equation 126.The output may be one of output source code 435 and a hardwareimplementation 495 such as semiconductor gates 445. In one embodiment,the output is executable code 440.

In one embodiment, the processor 405 may compile and execute the outputsource code 435 and the method 700 ends. In one embodiment, the compiledoutput source code 435 operates the hardware 496.

FIG. 6 is a schematic block diagram illustrating one embodiment of astate chart 600. In the depicted embodiment, the state chart 600 showseach logic state 205 is a state 160. In addition, the state chart 600shows state transitions 605 between each state 160.

Each state 160 may perform actions 174. In addition, each state 160 mayactivate another state 160, including the state 260 itself, based onconditional logic 172. Activating another state 160 is shown as a statetransition 605.

FIG. 7A is a graph 900 illustrating one embodiment of array complexity.The graph 900 shows an array size 905 for a multidimensional array ofthe source code 140 and an array size 910 for a corresponding lineararray 200 for multiple pairs of identical function implementations withvarious numbers of logic elements 176. For example, a first functionimplementation of 27 logic elements 176 may be implemented as a pair ofarrays comprising a multidimensional array and a linear array 200. Thearray size 905, 910 is shown on a log scale. Array size 905, 910 is onemeasure of array complexity and a good predictor of the computationaloverhead required to process an array.

The graph 900 illustrates that the array size 905 for multidimensionalarray implementations quickly becomes orders of magnitude larger thanthe corresponding array size 910 for linear array implementations. Byencoding the source code 140 as a linear array 200, array size isgreatly reduced, reducing the computational complexity of processing thelinear array 200.

FIG. 7B is a graph 915 illustrating one embodiment of speed improvements920 from identifying DON'T CARE assertion values 290. A percentage speedimprovement is shown as a result of identifying DON'T CARE assertionvalues 290 for minterms 240 of 4, 8, 12, and 15 logic states 205 of anexemplary linear array 200. The speed improvement 920 is calculated bycomparing processing time for the exemplary linear array 200 withoutidentifying the DON'T CARE assertion values 290, and the processing timefor the exemplary linear array 200 when DON'T CARE assertion values 290are identified for minterms 240 of 4, 8, 12, and 15 logic states 205 ofthe linear array 240 shown in Table 1. Table 1 shows an estimate ofprocessing time as a function of linear array size for minterms 240 of4, 8, 12, and 15 logic states 205 having either deasserted assertionvalues 290 or DON'T CARE assertion values 290.

TABLE 1 4 Logic 8 Logic 12 Logic 15 Logic States States States StatesDeasserted 645 499 362 251 DON'T CARE 547 369 216 78

FIGS. 8A-B are a schematic flowchart diagram illustrating one embodimentof a production array implementation method 800. The method 800 maygenerate the white box execution blocks 131, callable execution blocks151, intermediate linear arrays 153, and the production array 157. Inaddition, the method 800 may implement the production array 157 as oneor more of output source code 435, executable code 440, andsemiconductor gates 445. The method may be performed by one or moreprocessors 405 of the computer 400.

The method 800 starts, and in one embodiment, the processor 405identifies 801 a plurality of white box execution blocks 131 in thesource code 140. Each white box execution block 131 may be delimited bya begin block delimiter 344 and an end block delimiter 346. Theplurality of white box execution blocks 131 may be identified 801 fromthe parsed logic design of step 705 of FIG. 5B.

The processor 405 may identify 803 the state variables 133 for eachwhite box execution block 131. In addition, the processor 405 may name805 anonymous state variables 133. The anonymous state variables 133 maybe intermediate values without a given name in the source code 140.

The processor 405 may identify 807 a plurality of logically atomic codeblocks 341. Each logically atomic code block 341 may be a collection ofSLOC 173 that is executed sequentially from her, and logical condition172. The processor 405 may further append 809 each logically atomic codeblock 341 that modifies a given white box execution block 131 to thegiven white box execution block 131.

The processor 405 may determine 811 if each logically atomic code block341 that begins within the given white box execution block 131 also endswithin the given white box execution block 131. If each logically atomiccode block 341 that begins within the given white box execution block131 does not end within the white box execution block 131, the processor405 may loop to further identify 803 state variables 133 for the whitebox execution block 131 that would incorporate a logically atomic codeblock 341 that begins within the white box execution block 131 but doesnot end within the white box execution block 131.

If each logically atomic code block 341 that begins within the givenwhite box execution block 131 does end within the white box executionblock 131, the processor 405 generates 813 a callable execution block151 for each white box execution block 131. The callable execution block151 includes a next state value 230 and binary output variables 225 foreach combination of a present state values 220 and all binary inputvariables 215. In one embodiment, each next state value 230 comprisesspecified values for all state variables 133. The use of the callableexecution block 151 reduces the computational resources 425 required tocalculate the intermediate linear array 153.

The processor 405 may generate a do care array 139 for each callableexecution block 151. Each do care array 139 may further reduce thecomputational resources 425 required to calculate the intermediatelinear array 153.

In one embodiment, the processor 405 displays 819 one or more callableexecution blocks 151 as a finite state machine diagram 149. In addition,the processor 405 may display 821 the one or more callable executionblocks 151 as one or more transform boxes 330. The processor 405 mayreceive 823 modifications to the one or more callable execution blocks151 through the finite state machine diagrams 149 and/or the transformboxes 330.

The processor 405 may determine 825 the computational resources 425required to satisfy a minimization policy for minimizing the callableexecution blocks 151 and/or intermediate linear arrays 153. Theminimization policy may be based on the number of minterms 240associated with the callable execution blocks 151. In one embodiment,the minimization policy MP is satisfied if Equation 1 is satisfied,where CR is a number of computational resources 425.MP≤√CR  Equation 1

The processor 405 may allocate 827 computational resources 425 tosatisfy the minimization policy. The processor 405 may employ thecomputational resources 425 to generate 829 the intermediate lineararrays 153 from the callable execution blocks 151. The processor 405 mayfurther employ the computational resources 425 to generate 831 theproduction array 157. In one embodiment, the production array 157 isgenerated 831 by minimizing the intermediate linear arrays 153. Theintermediate linear arrays 153 may be minimized with a Quine-McCluskyalgorithm.

The processor 405 may implement 833 the production array 157. Theproduction array 157 may be implemented 833 as semiconductor gates 445.In addition, the production array 157 may be implemented 833 asminimized hardware output source code 435 such as a Verilog file. Theproduction array 157 may be implemented 833 as minimized output sourcecode 435. The minimized output source code 435 may be compiled and usedto operate hardware 496 as described in step 770 of FIG. 5C. Inaddition, the production array 157 may be implemented 833 as executablecode 440. The executable code 440 may be used to operate the hardware496.

FIG. 9 is a schematic flowchart diagram illustrating one embodiment of adifference identification method 950. The method 950 may identifydifferences in state variables 133 and binary output variables 225between an intermediate linear array 153 and a production array 157. Themethod 950 may be performed by one or more processors 405 of thecomputer 400.

The method 950 starts, and in one embodiment, the processor 405generates 951 at least one intermediate linear array 153. The at leastone intermediate linear array 153 may be generated 951 as described instep 829 of FIG. 8B. The processor 405 further generates 953 theproduction array 157. The production array 157 may be generated 953 asdescribed in step 831 of FIG. 8B.

The processor 405 may exercise 955 the at least one intermediate lineararray 153 and the production array 157 by assigning present state values220 and binary input variables 215 to each array 153/157. The processor405 may further identify 957 differences between the activation of thelogically atomic code block 341 and/or the Boolean equations of the atleast one intermediate linear array 153 and the production array 157 andthe method 950 ends.

The embodiments may include a method of implementing a production arraycomprising:

identifying, by use of a processor 405, a plurality of white boxexecution blocks 131 in source code 140, wherein each white boxexecution block 131 is delimited by a begin block delimiter 344 and ablock end delimiter 346.

identifying state variables 133 for each white box execution block 131,wherein each state variable 133 is Boolean, is only modified by thecorresponding white box execution block 131, and is modified at leastonce by the corresponding white box execution block 131;

identifying a plurality of logically atomic code blocks 341, whereineach logically atomic code block 341 is a collection of SLOC 173 that isexecuted sequentially from a common logical condition 172;

appending each logically atomic code block 341 that modifies a givenwhite box execution block 131 to the given white box execution block131, wherein each logically atomic code block 341 that begins within thegiven white box execution block 131 ends within the given white boxexecution block 131;

generating a callable execution block 151 for each white box executionblock 131, wherein the state variables 133 for callable execution blockcomprise callable source code parameters 137 and are globallymaintained, and the callable execution block 151 generates a next statevalue 230 and binary output variables 225 for each combination of apresent state values 220 and all binary input variables 215, whereineach next state value 230 comprises specified values for all statevariables 133;

generating a do care array 139 for each callable execution block 151,wherein each do care array 139 comprises a dimension 138 for all presentstate values 220 and each binary input variable 215 of the callableexecution block 131 and a binary do care/don't care value 141 for eachcombination of present state values 220 and binary input variableinstances 215;

displaying a behavior of a given callable execution block 151 as afinite state machine diagram 149;

displaying the behavior of the given callable execution block 151 as atransform box 330 showing binary input variables 215, binary outputvariables 225, present state values 220 and next state values 230 withthe associated Boolean sum of products of product of sums equation foreach state variable 133 and each binary output variables 225;

receiving modifications to one or more callable execution blocks 151;

generating the binary output variables 225 and computed next statevalues 230 for each combination of present state values 220 and binaryinput values 215 into an intermediate linear array 153, while excludingthose combinations of binary input values 215 that are don't cares.

generating a minimized production array 157 from the intermediate lineararray 153; and

implement the production array 157.

In one embodiment for the method of implementing the production array157, the intermediate linear array 153 comprises a logic state 205 forcallable execution block 151, each logic state 205 comprising one ormore binary output variables 225, one or more binary input variables215, one or more minterms 240 of the one or more binary input variables215, one or more maxterms 235 of the one or more minterms 240, one ormore present state values 220, and one or more next state values 230.

In one embodiment for the method of implementing the production array157, the production array 157 is implemented as semiconductor gates.

In one embodiment for the method of implementing the production array157, the production array 157 is implemented as one of minimizedhardware and software source code.

In one embodiment for the method of implementing the production array157, the production array 157 is implemented as executable code.

In one embodiment for the method of implementing the production array157, the method further comprises exercising the intermediate lineararray 153 and the production array 157; and identifying differences instate variables 133 and binary output values 225 between theintermediate linear array 153 and the production array 157.

In one embodiment for the method of implementing the production array157, the method further comprises determining computational resources425 required to satisfy a minimization policy; and allocating therequired computational resources 425.

In one embodiment for the method of implementing the production array157, the method further comprises naming anonymous state variables witha unique identifier.

The method of implementing the production array 157 may also beimplemented as a program product and an apparatus.

The embodiments parsed source code into a plurality of logic designelements 130. In addition, the embodiments identify the conditionallogic 172 in the computational logic 174 for each logic design element130. The embodiments encode each logic design element 130 as a logicstate 205 in the linear array 200. Because of the reduced complexity ofthe linear array 200, the source code is more easily analyzed andmanipulated.

Embodiments may be practiced in other specific forms. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the invention is, therefore, indicatedby the appended claims rather than by the foregoing description. Allchanges which come within the meaning and range of equivalency of theclaims are to be embraced within their scope.

What is claimed is:
 1. A method comprising: parsing, by use of aprocessor, source code of a multidimensional logical array logic designinto a plurality of logic design elements; identifying conditional logicfor each logic design element from the parsed source code; identifyingcomputation logic for each logic design element from the parsed sourcecode; identifying one or more next state values for each logic designelement from the parsed source code; encoding each logic design elementof the multidimensional logical array logic design as a logic state of aplurality of logic states in a linear array by assigning one or morepresent state values and the conditional logic for each logic designelement to each corresponding logic state, each logic state comprisingone or more binary output variables, one or more binary input variables,one or more minterms of the one or more binary input variables, one ormore maxterms of the one or more minterms, the one or more present statevalues, and the one or more next state values, wherein the plurality oflogic states are displayed as a plurality of fields in one or morecombination maps; organizing the plurality of binary input variablesinto the plurality of fields in the one or more combination maps;identifying logic relationships of the logic design from relationshiparrows in the one or more combination maps using the linear array;analyzing the logic relationships of the logic design using the one ormore combination maps of the linear array; and resolving the logicrelationships of the logic design using the one or more combination mapsof the linear array, wherein a linear array size is reduced; reducingthe logic relationships of the reduced logic design to a Booleanequation using the one or more combination maps; generating one ofminimized output source code and a minimized hardware implementationfrom the Boolean equation representation of the source code.
 2. Themethod of claim 1, the method further comprising: compiling the outputsource code; operating hardware with the compiled output source code. 3.The method of claim 1, the method further comprising displaying theplurality of logic states as a state chart.
 4. The method of claim 1,wherein parsing the source code comprises identifying nested loops. 5.The method of claim 4, wherein parsing the source code furthercomprises: identifying a first logic design element; inserting a beginblock delimiter; inserting an end block delimiter; and inserting adestination delimiter.
 6. The method of claim 1, wherein each logicdesign element comprises a logically atomic code block betweenconditional logic that does not contain a conditional logic.
 7. Themethod of claim 1, wherein each field of the plurality of fieldscorresponds to a respective display level of a multi-level displayformat having a top display level combination map and at least one lowerdisplay level combination map and the plurality of fields are furtherorganized by: selecting a first field of the plurality of fields, thefirst field corresponding to a first display level; identifyingcombinations of the binary input variables of a successive combinationmap that logically defines the first field of the plurality of fields,wherein the successive combination map is at a successive display levellower than the first display level; displaying at each successivedisplay level, combination maps of additional binary input variablesthat logically define the first field at each successive level until alast display level is reached; and converting the combination of binaryinput variables for each display level into a logical expression.
 8. Aprogram product comprising a non-transitory computer readable storagemedium storing code executable by a processor to perform: parsing sourcecode of a multidimensional logical array logic design into a pluralityof logic design elements; identifying conditional logic for each logicdesign element from the parsed source code; identifying computationlogic for each logic design element from the parsed source code;identifying one or more next state values for each logic design elementfrom the parsed source code; encoding each logic design element of themultidimensional logical array logic design as a logic state of aplurality of logic states in a linear array by assigning one or morepresent state values and the conditional logic for each logic designelement to each corresponding logic state, each logic state comprisingone or more binary output variables, one or more binary input variables,one or more minterms of the one or more binary input variables, one ormore maxterms of the one or more minterms, the one or more present statevalues, and the one or more next state values, wherein the plurality oflogic states are displayed as a plurality of fields in one or morecombination maps; organizing the plurality of binary input variablesinto the plurality of fields in the one or more combination maps;identifying logic relationships of the logic design from relationshiparrows in the one or more combination maps using the linear array;analyzing the logic relationships of the logic design using the one ormore combination maps of the linear array; and resolving the logicrelationships of the logic design using the one or more combination mapsof the linear array, wherein a linear array size is reduced; reducingthe logic relationships of the reduced logic design to a Booleanequation using the one or more combination maps; generating one ofminimized output source code and a minimized hardware implementationfrom the Boolean equation representation of the source code.
 9. Theprogram product of claim 8, the processor further: compiling the outputsource code; operating hardware with the compiled output source code.10. The program product of claim 8, the processor further displaying theplurality of logic states as a state chart.
 11. The program product ofclaim 8, wherein parsing the source code comprises identifying nestedloops.
 12. The program product of claim 11, wherein parsing the sourcecode further comprises: identifying a first logic design element;inserting a begin block delimiter; inserting an end block delimiter; andinserting a destination delimiter.
 13. The program product of claim 8,wherein each logic design element comprises a logically atomic codeblock between conditional logic that does not contain a conditionallogic.
 14. The program product of claim 8, wherein each field of theplurality of fields corresponds to a respective display level of amulti-level display format having a top display level combination mapand at least one lower display level combination map and the pluralityof fields are further organized by: selecting a first field of theplurality of fields, the first field corresponding to a first displaylevel; identifying combinations of the binary input variables of asuccessive combination map that logically defines the first field of theplurality of fields, wherein the successive combination map is at asuccessive display level lower than the first display level; displayingat each successive display level, combination maps of additional binaryinput variables that logically define the first field at each successivelevel until a last display level is reached; and converting thecombination of binary input variables for each display level into alogical expression.
 15. An apparatus comprising: a processor: a memorystoring code executable by a processor to perform: parsing source codeof a multidimensional logical array logic design into a plurality oflogic design elements; identifying conditional logic for each logicdesign element from the parsed source code; identifying computationlogic for each logic design element from the parsed source code;identifying one or more next state values for each logic design elementfrom the parsed source code; encoding each logic design element of themultidimensional logical array logic design as a logic state of aplurality of logic states in a linear array by assigning one or morepresent state values and the conditional logic for each logic designelement to each corresponding logic state, each logic state comprisingone or more binary output variables, one or more binary input variables,one or more minterms of the one or more binary input variables, one ormore maxterms of the one or more minterms, the one or more present statevalues, and the one or more next state values, wherein the plurality oflogic states are displayed as a plurality of fields in one or morecombination maps; organizing the plurality of binary input variablesinto the plurality of fields in the one or more combination maps;identifying logic relationships of the logic design from relationshiparrows in the one or more combination maps using the linear array;analyzing the logic relationships of the logic design using the one ormore combination maps of the linear array; and resolving the logicrelationships of the logic design using the one or more combination mapsof the linear array, wherein a linear array size is reduced; reducingthe logic relationships of the reduced logic design to a Booleanequation using the one or more combination maps; generating one ofminimized output source code and a minimized hardware implementationfrom the Boolean equation representation of the source code.
 16. Theapparatus of claim 15, the processor further: compiling the outputsource code; operating hardware with the compiled output source code.17. The apparatus of claim 15, the processor further displaying theplurality of logic states as a state chart.
 18. The apparatus of claim15, wherein parsing the source code comprises identifying nested loops.19. The apparatus of claim 18, wherein parsing the source code furthercomprises: identifying a first logic design element; inserting a beginblock delimiter; inserting an end block delimiter; and inserting adestination delimiter.
 20. The apparatus of claim 15, wherein each logicdesign element comprises a logically atomic code block betweenconditional logic that does not contain a conditional logic.